Quickchip develops different cores for a broad range of requirements. The cores are designed for FPGA implementation and, thus, are delivered as EDIF net lists taylored for different FPGA device families. The first core released so far ist the QUIC_8051.
||Intel (R) 8051 compatible embedded controller. This standard embedded controller core consists of the CPU, 256 Bytes of RAM, three timers/counters, the UART, and the two-level interrupt controller.
||Same as QUIC_8051 but with on-chip debug module accessible through JTAG interface.